The thin-film transistor (TFT) is a type of field-effect transistor whose layers are formed from thin films deposited on a substrate. TFTs have many useful and popular applications such as active-matrix liquid-crystal displays (LCDs) and 3-dimensional integrated circuits.
TFTs are typically formed by depositing an insulator on a substrate layer. A thin-film semiconducting layer is deposited onto the insulating layer. Source and drain regions are formed within the semiconducting layer by doping either p- or n-type impurities depending on the type of TFT being formed. A typical TFT has a gate-modulated channel region located between the source and drain regions.
As with other implementations of metal-oxide-semiconductor field-effect transistors (MOSFETs), of which TFTs are an example, TFTs generally incorporate n- or p-type impurities, such as phosphorus or boron respectively, into the source and drain regions of a transistor by implantation or diffusion. Because of the need to activate implanted impurities and to tailor the depth of implanted or diffused junctions, a high-temperature annealing step is generally required subsequent to the introduction of the impurities.
Advanced TFT devices such as those used in advanced displays, generally require a continued reduction in the TFT channel length and the active island thickness of a TFT. Moreover, advanced TFT devices demand enhanced TFT performance such as high on-state current for providing high contrast ratio and high switching speed, particularly for displays based on organic light-emitting diodes. As the channel length and active island thickness are reduced, device performance is increasingly degraded by the source and drain parasitic resistance.
The problem of high source/drain resistance is further aggravated in thin-film transistors with ultra-thin active layers, which are typically implemented to achieve better gate-control for reduced short-channel effects. For polycrystalline silicon based TFTs fabricated on low-temperature glass substrates for display applications, the parasitic resistance is aggravated by the necessity to maintain a relatively low temperature of activation and the trapping of carriers in grain boundaries.
In addition to displays, advanced TFTs may be used for the realization of high-performance scaled transistors, particularly those based on thin-film type silicon-on-insulator substrates or narrow thin-film type structures such as FINFETs. The accompanying high source and drain parasitic resistance, if not alleviated, would degrade the performance of the resulting integrated circuits.
Various techniques have been employed to minimize source and drain resistance. For example, the source and drain regions may undergo silicidation or thickening. While such techniques have been effective at lowering source and drain resistance, these techniques result in increased process complexity and increased manufacturing cost.
Two popular ways of forming a MOSFET with raised source and drain regions are the selective epitaxial growth and the deposition of silicon. After the formation of doped source/drain regions, gate-edge spacers are formed. Selective epitaxial growth or selective deposition is used to form a raised silicon structure on the source and drain regions. Selectivity is typically difficult to control and requires expensive equipment.
Techniques in the related art have sought to lower source and drain resistance by using metallic source and drain electrodes. For example, U.S. Patent Application Publication No. 2005/0104152 (Snyder) uses metal silicides to form Schottky barrier or Schottky-like contacts to the semiconductor substrate. This metal silicidation process lacks the desired performance characteristics and simplicity of process. Moreover, silicidation techniques typically require an activation temperature above 500° C. and after the silicidation, any remaining unreacted metal must be removed.
Additionally, U.S. Pat. No. 6,555,879 (Krivokapic) relates to the use of metal with the source and drain. However, Krivokapic, like Snyder, uses an undesirable metal silicidation process. Thus, a more effective and simpler method for reducing source and drain resistance is desired.
Accordingly, there is a strong demand for TFTs with low source and drain resistance, and preferably fabricated at a temperature below 500° C. and compatible with inexpensive glass substrates.